Senior DFT Engineer (M/W)
Opportunities to learn and develop both technically and personaly are aplenty here! Our recruitment process consists of tests and about 3 interviews.
![bandeau FT120 (002).jpg](https://images.teamtailor-cdn.com/images/s3/teamtailor-production/gallery_picture-v6/image_uploads/cf5f66ef-f8ef-4821-a146-29aa3f1f1b4e/original.jpeg)
❓ About SiPearl…
Founded in 2019 with the support of the European Union 🇪🇺, SiPearl embodies Europe's dream of mastering the technological heart of its supercomputers: the microprocessor.
SiPearl is building Rhea, the high-performance, low-power European microprocessor dedicated to supercomputing and AI inference.
This new generation of microprocessors will first target EuroHPC Joint Undertaking ecosystem, which is deploying world-class supercomputing infrastructures in Europe for solving major challenges in medical research, artificial intelligence, security, energy management and climate with a reduced carbon footprint.
SiPearl is working in close collaboration with its 30 partners from the European Processor Initiative (EPI) consortium - leading names from the scientific community, supercomputing centers and industry - which are its stakeholders, future clients and end-users.
SiPearl employs more than 190 people in:
- France (Maisons-Laffitte, Grenoble, Massy, Sophia Antipolis),
- Germany (Duisburg)
- Spain (Barcelona)
- and Italy (Bologna)
SiPearl is part of French Tech Next 120 programme 2024 class.
🎯 What a regular day at the job might look like:
- Prediction of fault-models, estimation of yield and creation of innovative DfT strategies
- Work with the system architecture team to implement the DfT concept
- Generate ATE structural and functional test-pattern by use of RTL strobing and Gatelevel-Resimulation
- Predict and optimize ATE test-time
- Identify, generate and integrate the DfT IPs needed on RTL and Netlist level
- Perform functional verification of DfT structures in RTL level
- Perform test-specific verification and coverage analysis of DfT structures in RTL level and Netlist level
- Work with IP design teams locally or remotely
- Work with verification teams locally or remotely
- Work with ASIC service company for chip implementation in different timezones
🔍 What would make you succeed in this role:
- Graduate from an engineer school or from a Master (5 years diploma post baccalauréat)
- At least 10 years knowledge in DfT concept and implementation on RTL and/or Netlist level
- At least 10 years knowledge in Scan-Insertion (all types), MBIST, IJTAG, Boundary-Scan
- At least 5 years of knowledge working towards ATE team
- Management skills
- Experience in aligning with production-fab, understanding their yield parameters
- Experience in split-lot and shmoo analysis and failure detection in silicon
- Experience in RTL simulation/verification and associated environment
- Experience in interaction with constraint development for logical synthesis
- Experience in most of the tools: RTL compiler, Testkompress/Tetramax, Virage/Mentor, memory Bist, Mentor Bscan, Mentor SSN, Formal Equivalence tools, Nc-sim/questa-sim, revision control (git..)
- Gained some exposure to digital ASIC front and backend design & verification processes
- Good scripting skills, e.g. using TCL/Perl/Phyton
- Good problem-solving capability
- Ability to document and train others on work developed
- Excellent oral and writing English communication
Recruitment process
✔️Discovery interview with our Talent Acquisition Partner (30')
✔️ Personality test - no need to worry, there is no wrong or right answer; our goal is to get to see beyond your resume (45')
✔️ 2 Technical discussions (1h each)
✔️ Interview with an HRBP (1h)
💡 Benefits and conditions :
- Contract: Permanent Contract (CDI)
- Benefits: annual bonus; meal vouchers (60% covered by SiPearl); health insurance (70% covered by SiPearl); 5 days per year of remote work from any EU location; illimited access and pre-paid sessions with a practitioner of your choice on our mental health partner app, moka.care; technical, linguistic and personal development trainings; BSPCE/ stock options
- Work model: Hybrid (2 days/week remote)
- 📍 Office: This role is open for our locations
in France (Maisons-Laffitte, Massy, Grenoble and Sophia Antipolis),
Spain (Barcelona) and Germany (Duisburg)
- Awesome activities such as: Hackathons, Training Challenges, Quarterly Kick-off sessions, team events, Company events and much more
- ⚠️ Please note that while we do not provide VISA Sponsorship, we are committed to assisting international candidates with the visa application process to the best of our ability.
Are you curious to learn more about us?
- Follow us on LinkedIn to stay updated with our latest news
- Get updated about our recruiting activities: Sipearl careers webpage
- Get to know a bit more about our team culture: Welcome to the jungle
At SiPearl, we are dedicated to building a diverse and inclusive workplace that thrives on the strength of varied perspectives and backgrounds. We recruit talent based on merit, experience, and alignment with our company's goals and values.
- Department
- Hardware
- Role
- Design For Test (DFT)
- Locations
- Grenoble , Barcelona, Maisons-Laffitte, Massy , Valbonne Sophia Antipolis , Duisburg
- Remote status
- Hybrid
About SiPearl
Whether senior or junior engineers; whether specializing in embedded firmware, microelectronics design, virtual prototyping, modeling & simulation or software development, the SiPearl team works with the best of global microprocessor technologies: multi-core architecture, Neoverse® V1 platform from industry leader ARM, 6nm fabrication process,
Senior DFT Engineer (M/W)
Opportunities to learn and develop both technically and personaly are aplenty here! Our recruitment process consists of tests and about 3 interviews.
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